FIG. 1A illustrates a memory device 100 in which conventional timing techniques for bitline pre-charging and wordline operations are employed. The device 100 includes a timing controller 110, pre-charge and wordline drivers PCLD and WL0-mD 120, respectively, pre-charge circuits PC0-n 130 coupled along a pre-charge line PCL, and memory cells 140 coupled as shown to n+1 pairs of bitlines BL and /BL and m+1 wordlines WL0-m.
Timing controller 110 is operable to receive a control signal 112, e.g., a signal to activate a data read or write operation of a particular memory cell, and responsive thereto, generates a wordline triggering signal 116 for activating the wordline of the selected cell, and a pre-charge triggering signal 118. The wordline triggering signal 116 output from the timing controller 110 is operable to activate the wordline driver of the selected memory cell, the wordline driver operable to apply a desired wordline voltage on the selected cell's wordline. The pre-charge triggering signal 118 is operable to activate the pre-charge driver PCLD, which in turn operates to pre-charge (or discontinue pre-charging) the bitlines. The timing controller 110 controls the timing of the activation and deactivation of the pre-charge and wordlines, typically through the use of preset delays.
FIG. 1B illustrates a conventional process in which a memory cell read or write process is performed using the memory device 100 of FIG. 1A. Initially at 171, a previously activated bitline pre-charging process is stopped. At 172, a first predefined delay period is executed, and subsequent at 173, a selected wordline activated. Next at 174, a second predefined delay period is executed, after which at 175 read or write operations are performed. At 176 the selected wordline is deactivated, and at 177 a third predefined delay period is executed. At 178, the array bitlines are pre-charged in preparation for a subsequent read or write operation, and at 179, a fourth predetermined delay period is executed before deactivating bitline pre-charging circuits for the next read/write operation.
As can be understood from FIG. 1B, the total time needed for a read or write operation is heavily dependent upon the delay periods 172, 174, 176, and 179. In particular, it is important to minimize these delay periods in order to decrease the total time needed for a read or write operation.
While it is important to reduce the delay periods, it is also important that the periods be of sufficient duration so as not to interfere with the data reading or writing processes. In particular, each operation must be permitted to fully complete the subsequent operation in order for the read or write process to accurately conclude. Further, the delay period allocated for these processes must take into account possible operating condition extremes and process variations, which could further impact the timing of the illustrated processes.
In order to address this problem, a conventional approach presently used is the allocation of a first delay ΔF for the generation of a bitline pre-charge triggering signal needed in processes 172 and 179, and a second delay ΔR for the generation of a wordline triggering signal needed in processes 174 and 176. Unfortunately, the predetermined delay periods are not optimized for the particular memory device, and typically represent the worst possible process variations and operating conditions under which the memory device is fabricated and operated. Because the excess delay times are built into the memory devices, it is usually not possible to attain faster reading and writing speeds, even if the memory device is otherwise capable of doing so.
What is therefore needed is an improved memory device architecture and corresponding method for timing wordline and bitline charging operations, which enable shorter delay times.